94 lines
2.1 KiB
Systemverilog
94 lines
2.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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// Check that an enum value is one of the valid members
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`define check_enum_color(gotv) \
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if ((gotv) !== RED && (gotv) !== GREEN && (gotv) !== BLUE) begin \
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$write("%%Error: %s:%0d: invalid color=%0d\n", `__FILE__, `__LINE__, (gotv)); \
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`stop; \
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end
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`define check_enum_state(gotv) \
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if ((gotv) !== IDLE && (gotv) !== RUN && (gotv) !== STOP) begin \
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$write("%%Error: %s:%0d: invalid state=%0d\n", `__FILE__, `__LINE__, (gotv)); \
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`stop; \
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end
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module t;
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typedef enum logic [1:0] {
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RED = 2'd0,
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GREEN = 2'd1,
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BLUE = 2'd2
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} color_e;
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typedef enum logic [2:0] {
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IDLE = 3'd0,
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RUN = 3'd3,
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STOP = 3'd5
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} state_e;
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class InnerObj;
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rand color_e color;
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rand state_e state;
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endclass
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class OuterObj;
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rand InnerObj inner;
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function new();
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inner = new();
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endfunction
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endclass
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// Nested: TopObj -> MiddleObj -> InnerObj
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class MiddleObj;
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rand InnerObj inner;
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function new();
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inner = new();
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endfunction
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endclass
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class TopObj;
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rand MiddleObj mid;
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function new();
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mid = new();
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endfunction
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endclass
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initial begin
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OuterObj obj;
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TopObj top;
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obj = new();
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top = new();
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// Test direct sub-object enum (one level deep)
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repeat (20) begin
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`checkd(obj.randomize(), 1)
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`check_enum_color(obj.inner.color)
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`check_enum_state(obj.inner.state)
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end
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// Test nested sub-object enum (two levels deep)
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repeat (20) begin
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`checkd(top.randomize(), 1)
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`check_enum_color(top.mid.inner.color)
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`check_enum_state(top.mid.inner.state)
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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