116 lines
2.2 KiB
Systemverilog
116 lines
2.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2014 Jie Xu
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// SPDX-License-Identifier: CC0-1.0
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// change these two parameters to see the speed differences
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`define DATA_WIDTH 8
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`define REP_COUNT4 `DATA_WIDTH/4
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`define REP_COUNT2 `DATA_WIDTH/2
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module t (
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input clk
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);
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reg [3:0] count4 = 0;
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reg [1:0] count2 = 0;
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reg [`DATA_WIDTH-1:0] a = {`REP_COUNT4{4'b0000}};
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reg [`DATA_WIDTH-1:0] b = {`REP_COUNT4{4'b1111}};
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reg [`DATA_WIDTH-1:0] c = {`REP_COUNT4{4'b1111}};
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reg [`DATA_WIDTH-1:0] d = {`REP_COUNT4{4'b1111}};
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reg [`DATA_WIDTH-1:0] res1;
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reg [`DATA_WIDTH-1:0] res2;
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reg [`DATA_WIDTH-1:0] res3;
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reg [`DATA_WIDTH-1:0] res4;
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drv1 t_drv1[`DATA_WIDTH-1:0] (
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.colSelA(a),
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.datao(res1)
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);
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drv2 t_drv2[`DATA_WIDTH-1:0] (
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.colSelA(a),
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.colSelB(b),
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.datao(res2)
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);
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drv3 t_drv3[`DATA_WIDTH-1:0] (
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.colSelA(a),
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.colSelB(b),
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.colSelC(c),
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.datao(res3)
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);
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drv4 t_drv4[`DATA_WIDTH-1:0] (
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.colSelA(a),
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.colSelB(b),
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.colSelC(c),
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.colSelD(d),
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.datao(res4)
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);
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always @(posedge clk) begin
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count2 <= count2 + 1;
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count4 <= count4 + 1;
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a <= {`REP_COUNT4{count4}};
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b <= {`REP_COUNT4{count4}};
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c <= {`REP_COUNT2{count2}};
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d <= {`REP_COUNT2{count2}};
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if (res1 != (a)) begin
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$stop;
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end
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if (res2 != (a & b)) begin
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$stop;
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end
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if (res3 != (a & b & c)) begin
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$stop;
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end
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if (res4 != (a & b & c & d)) begin
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$stop;
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end
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if (count4 > 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module drv1 (
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input colSelA,
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output datao
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);
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assign datao = colSelA;
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endmodule
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module drv2 (
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input colSelA,
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input colSelB,
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output datao
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);
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assign datao = colSelB & colSelA;
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endmodule
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module drv3 (
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input colSelA,
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input colSelB,
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input colSelC,
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output datao
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);
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assign datao = colSelB & colSelA & colSelC;
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endmodule
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module drv4 (
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input colSelA,
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input colSelB,
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input colSelC,
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input colSelD,
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output datao
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);
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assign datao = colSelB & colSelA & colSelC & colSelD;
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endmodule
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