45 lines
980 B
Systemverilog
45 lines
980 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2009 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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localparam UADDR_WIDTH = 4'd10;
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localparam UROM_WIDTH = 5'd17;
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localparam UROM_DEPTH = 11'd1024;
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module t (
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input clk,
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input [UADDR_WIDTH-1:0] mAddr,
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output logic [UROM_WIDTH-1:0] mOutput
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);
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// Issue #3959
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reg [UROM_WIDTH-1:0] uRam[UROM_DEPTH];
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always @(posedge clk) mOutput <= uRam[mAddr];
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// Issue #6045
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typedef enum logic [1:0] {
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e_0,
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e_1,
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e_2,
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e_3
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} enum_e;
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typedef struct packed {
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integer unsigned x;
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integer unsigned y;
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} foo_s;
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typedef struct packed {integer unsigned y;} bar_s;
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// Warning due to concatenation, but this is actually a member assignment
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localparam foo_s FOO = '{y: (1 << e_0) | (1 << e_3), default: '0};
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// No warning
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localparam bar_s BAR = '{y: (1 << e_0) | (1 << e_3)};
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endmodule
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