55 lines
933 B
Systemverilog
55 lines
933 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2014 Jie Xu
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// SPDX-License-Identifier: CC0-1.0
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//bug692
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module t ( /*AUTOARG*/
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// Inputs
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clk
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);
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input wire clk;
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wire [31:0] result;
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test_if #(.ID(3)) s ();
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sub_test U_SUB_TEST (
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s.a.b,
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result
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); // the line causing error
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endmodule : t
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// ---------------------------------------------------------------------------
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module sub_test (
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input [31:0] b,
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output [31:0] c
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);
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assign c = b;
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endmodule
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// ---------------------------------------------------------------------------
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interface test_if #(
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parameter ID = 0
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) ();
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typedef struct packed {
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logic a;
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logic [31:0] b;
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} aType;
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aType a;
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typedef struct packed {
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logic c;
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logic [31:0] d;
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} bType;
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bType b;
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modport master(input a, output b);
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endinterface
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