34 lines
800 B
Systemverilog
34 lines
800 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2014 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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interface pads_if ();
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modport mp_dig(import fIn, import fOut);
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integer exists[8];
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function automatic integer fIn(integer i);
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fIn = exists[i];
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endfunction
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task automatic fOut(integer i);
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exists[i] = 33;
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endtask
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endinterface
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module t;
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pads_if padsif[1:0] ();
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pads_if padsif_arr[1:0] ();
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initial begin
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padsif[0].fOut(3);
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if (padsif[0].fIn(3) != 33) $stop;
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padsif_arr[0].fOut(3);
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if (padsif_arr[0].fIn(3) != 33) $stop;
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padsif_arr[1].fOut(3);
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if (padsif_arr[1].fIn(3) != 33) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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