81 lines
1.5 KiB
Systemverilog
81 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2013 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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interface ifc;
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integer value;
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endinterface
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module t (
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input clk
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);
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`ifdef INLINE_A //verilator inline_module
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`else //verilator no_inline_module
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`endif
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integer cyc = 1;
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ifc itop1a ();
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ifc itop1b ();
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ifc itop2a ();
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ifc itop2b ();
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wrapper c1 (
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.isuba(itop1a),
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.isubb(itop1b),
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.i_valuea(14),
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.i_valueb(15)
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);
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wrapper c2 (
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.isuba(itop2a),
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.isubb(itop2b),
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.i_valuea(24),
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.i_valueb(25)
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);
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 20) begin
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if (itop1a.value != 14) $stop;
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if (itop1b.value != 15) $stop;
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if (itop2a.value != 24) $stop;
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if (itop2b.value != 25) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module wrapper (
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ifc isuba,
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ifc isubb,
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input integer i_valuea,
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input integer i_valueb
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);
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`ifdef INLINE_B //verilator inline_module
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`else //verilator no_inline_module
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`endif
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lower subsuba (
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.isub(isuba),
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.i_value(i_valuea)
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);
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lower subsubb (
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.isub(isubb),
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.i_value(i_valueb)
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);
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endmodule
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module lower (
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ifc isub,
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input integer i_value
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);
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`ifdef INLINE_C //verilator inline_module
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`else //verilator no_inline_module
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`endif
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always @* begin
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isub.value = i_value;
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end
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endmodule
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