32 lines
651 B
Systemverilog
32 lines
651 B
Systemverilog
// DESCRIPTION: Verilator: Functionally demonstrate an array of interfaces
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2017 Mike Popoloski
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// SPDX-License-Identifier: CC0-1.0
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interface foo_intf (
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input x
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);
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endinterface
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module foo_subm (
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input x
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);
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endmodule
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module t;
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localparam N = 3;
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wire [2:0] X = 3'b110;
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// Will cause ASCRANGE warning?
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foo_intf foos[N] (.x(X)); // bad
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foo_intf fool[1:3] (.x(X)); // bad
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foo_intf foom[3:1] (.x(X)); // ok
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foo_subm subs[N] (.x(X)); // bad
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foo_subm subl[1:3] (.x(X)); // bad
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foo_subm subm[3:1] (.x(X)); // ok
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endmodule
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