50 lines
780 B
Systemverilog
50 lines
780 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2012 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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logic foo;
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initial foo = 0;
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// dut #(.W(4)) udut(.*);
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dut #(
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.W(4)
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) udut (
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.clk(clk),
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.foo(foo)
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); // Assigning logic to logic array
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endmodule
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module dut #(
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parameter W = 1
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) (
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input logic clk,
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input logic foo[W-1:0]
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);
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genvar i;
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generate
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for (i = 0; i < W; i++) begin
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suba ua (
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.clk(clk),
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.foo(foo[i])
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);
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end
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endgenerate
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endmodule
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module suba (
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input logic clk,
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input logic foo
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);
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always @(posedge clk) $display("foo=%b", foo);
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endmodule
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