84 lines
1.4 KiB
Systemverilog
84 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2017 John Stevenson
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// SPDX-License-Identifier: CC0-1.0
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typedef logic [63:0] uid_t;
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typedef logic [31:0] value_t;
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interface the_intf #(
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parameter M = 5
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);
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logic valid;
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uid_t uid;
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value_t [M-1:0] values;
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modport i(output valid, output uid, output values);
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modport t(input valid, input uid, input values);
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endinterface
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module Contemplator #(
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parameter IMPL = 0,
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parameter M = 5,
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parameter N = 1
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) (
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input logic clk,
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the_intf.i out[N-1:0]
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);
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the_intf #(.M(M)) inp[N-1:0] ();
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DeepThought #(
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.N(N)
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) ultimateAnswerer (
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.src(inp),
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.dst(out)
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);
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endmodule
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module DeepThought #(
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parameter N = 1
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) (
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the_intf.t src[N-1:0],
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the_intf.i dst[N-1:0]
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);
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endmodule
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module t ( /*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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localparam M = 5;
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localparam N = 1;
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the_intf #(.M(M)) out0[N-1:0] ();
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the_intf #(.M(M)) out1[N-1:0] ();
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Contemplator #(
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.IMPL(0),
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.M(M),
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.N(N)
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) contemplatorOfTheZerothKind (
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.clk(clk),
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.out(out0)
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);
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Contemplator #(
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.IMPL(1),
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.M(M),
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.N(N)
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) contemplatorOfTheFirstKind (
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.clk(clk),
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.out(out1)
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);
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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