104 lines
2.3 KiB
Systemverilog
104 lines
2.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2011 Jeremy Bennett
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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// verilator lint_off MULTIDRIVEN
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wire [19:10] bitout;
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// verilator lint_on MULTIDRIVEN
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wire [29:24] short_bitout;
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wire [7:0] allbits;
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wire [15:0] twobits;
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sub
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i_sub1[7:4] (
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.allbits(allbits),
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.twobits(twobits[15:8]),
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.bitout(bitout[17:14])
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),
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i_sub2[3:0] (
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.allbits(allbits),
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.twobits(twobits[7:0]),
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.bitout(bitout[13:10])
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);
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sub i_sub3[7:4] (
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.allbits(allbits),
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.twobits(twobits[15:8]),
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.bitout(bitout[17:14])
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);
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sub i_sub4[7:4] (
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.allbits(allbits),
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.twobits(twobits[15:8]),
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.bitout(short_bitout[27:24])
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);
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sub i_sub5[7:0] (
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.allbits(allbits),
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.twobits(twobits),
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.bitout(bitout[17:10])
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);
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sub i_sub6[7:4] (
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.allbits(allbits),
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.twobits(twobits[15:8]),
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.bitout({bitout[18+:2], short_bitout[28+:2]})
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);
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integer cyc = 0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Signals under test
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assign allbits = crc[7:0];
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assign twobits = crc[15:0];
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wire [63:0] result = {48'h0, short_bitout, bitout};
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// Test loop
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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if (cyc == 0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 64'h0;
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end
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else if (cyc < 10) begin
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sum <= 64'h0;
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end
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else if (cyc < 90) begin
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end
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else if (cyc == 99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'ha1da9ff8082a4ff6
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule // t
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module sub (
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input wire [7:0] allbits,
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input wire [1:0] twobits,
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output wire bitout
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);
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assign bitout = (^twobits) ^ (^allbits);
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endmodule // sub
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