37 lines
632 B
Systemverilog
37 lines
632 B
Systemverilog
// DESCRIPTION: Verilator: Simple test of unoptflat
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2013 Jeremy Bennett
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// SPDX-License-Identifier: CC0-1.0
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localparam ID_MSB = 1;
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module t (
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input clk
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);
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typedef struct packed {logic [1:0] id;} context_t;
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context_t tsb;
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assign tsb.id = {tsb.id[0], clk};
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initial begin
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tsb.id = 0;
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end
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always @(posedge clk or negedge clk) begin
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`ifdef TEST_VERBOSE
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$write("tsb.id = %x\n", tsb.id);
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`endif
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if (tsb.id[1] != 0) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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