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61 lines
1.3 KiB
Systemverilog
61 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Goekce Aydos
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// SPDX-License-Identifier: CC0-1.0
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// Interface instantiation without parenthesis
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interface intf_no_instance;
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endinterface
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interface intf #(
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parameter int par
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);
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logic in;
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modport A(input in);
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endinterface
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module b (
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intf intf_b_port,
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intf.A intf_b_port_mod
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);
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intf intf_b_not_port;
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intf.A intf_b_not_port_mod;
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intf_no_instance intf_no_instance_b_not_port;
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endmodule
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module d (intf_d_port, intf_d_port_mod);
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intf intf_d_port;
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intf intf_d_not_port;
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intf.A intf_d_port_mod;
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intf.A intf_d_not_port_mod;
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intf_no_instance intf_no_instance_d_not_port;
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endmodule
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module t;
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intf intf_t_not_port;
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intf.A intf_t_not_port_mod;
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intf_no_instance intf_no_instance_t_not_port;
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intf #(.par(8)) intf_exists();
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b b1 (
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.intf_b_port(intf_exists),
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.intf_b_port_mod(intf_exists.A),
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.intf_b_not_port(intf_exists.A)
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);
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b b2 (
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.intf_b_port(intf_exists),
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.intf_b_port_mod(intf_exists.A)
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);
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d d1 (
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.intf_d_port(intf_exists),
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.intf_d_port_mod(intf_exists.A),
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.intf_d_not_port(intf_exists.A)
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);
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d d2 (
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.intf_d_port(intf_exists),
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.intf_d_port_mod(intf_exists.A)
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);
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initial $finish;
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endmodule
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