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88 lines
2.1 KiB
Systemverilog
88 lines
2.1 KiB
Systemverilog
// DESCRIPTION: Verilator: System Verilog test of array querying functions.
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//
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// This code instantiates a module that calls the various array querying
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// functions.
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2012 Jeremy Bennett, Embecosm
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t (
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input clk
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);
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wire a = clk;
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wire b = 1'b0;
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reg c;
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array_test array_test_i ( /*AUTOINST*/
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// Inputs
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.clk(clk)
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);
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endmodule
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// Check the array sizing functions work correctly.
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module array_test #(
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parameter LEFT = 5,
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RIGHT = 55
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) ( /*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// verilator lint_off ASCRANGE
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reg [7:0] a[LEFT:RIGHT];
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// verilator lint_on ASCRANGE
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typedef reg [7:0] r_t;
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typedef r_t array_t[LEFT:RIGHT];
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task automatic query_dimensions(input int dimension, output int left_bound, right_bound,
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array_size);
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// verilator no_inline_task
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left_bound = $left(array_t, dimension);
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right_bound = $right(array_t, dimension);
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array_size = $size(array_t, dimension);
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endtask
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integer l;
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integer r;
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integer s;
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int cycle = 0;
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always @(posedge clk) begin
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l = $left(a);
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r = $right(a);
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s = $size(a);
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`ifdef TEST_VERBOSE
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$write("$left (a) = %d, $right (a) = %d, $size (a) = %d\n", l, r, s);
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`endif
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if ((l != LEFT) || (r != RIGHT) || (s != (RIGHT - LEFT + 1))) $stop;
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if ($left(r_t) != 7 || $right(r_t) != 0 || $size(r_t) != 8 || $bits(r_t) != 8) $stop;
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// A runtime dimension selects entries in compiler-generated constant tables.
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query_dimensions(cycle[0] ? 2 : 1, l, r, s);
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`checkd(l, cycle[0] ? 7 : LEFT);
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`checkd(r, cycle[0] ? 0 : RIGHT);
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`checkd(s, cycle[0] ? 8 : RIGHT - LEFT + 1);
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cycle <= cycle + 1;
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if (cycle == 3) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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