32 lines
612 B
Systemverilog
32 lines
612 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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class C;
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task f;
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int x = 0;
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fork
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#6 x = 4;
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#2 x++;
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x = #4 x * 3;
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begin
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#1 if (x != 1) $stop;
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#2 if (x != 2) $stop;
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#2 if (x != 3) $stop;
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#2 if (x != 4) $stop;
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$finish;
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end
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join_none
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x = 1;
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endtask
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endclass
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initial begin
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C o = new;
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o.f;
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end
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endmodule
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