verilator/test_regress
Lukasz Dalek d6ac351dcb Add --public-flat-rw switch, bug1511.
This switch exposes VARs, PORTs and WIREs to C++ code. It must be use
with care as it has a significant performance impact and may result in
mis-simulation of generated clocks. Anyhow, it is prefered over
--public and useful for VPI.

Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
Signed-off-by: Stefan Wallentowitz <stefan@wallentowitz.de>
Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>
2019-09-23 07:56:07 -04:00
..
t Add --public-flat-rw switch, bug1511. 2019-09-23 07:56:07 -04:00
.gdbinit Debug: Add default .gdbinit file 2012-03-02 20:59:47 -05:00
.gitignore Add XSim support to driver.pl, bug1493. 2019-08-29 17:00:49 -04:00
Makefile Tests: Default test_regress to quiet 2019-07-14 15:04:19 -04:00
Makefile_obj Copyright year update. 2019-01-03 19:17:22 -05:00
driver.pl Tests: Set VM_PREFIX from test script. 2019-09-21 08:26:34 -04:00
input.vc Tests: Check for and remove trailing newlines 2019-05-13 19:47:52 -04:00
input.xsim.vc Add XSim support to driver.pl, bug1493. 2019-08-29 17:00:49 -04:00
vgen.pl Internals: Detab and fix spacing style issues in tests and scripts. No functional change. 2019-05-07 22:34:09 -04:00