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https://github.com/verilator/verilator.git
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Geza Lore
eafe9636cf
Remove the expression combination counts from the default stats file, and add a new `--dump-ast-patterns` option, which will dump new `*_ast_patterns_*.txt` files. These contain the expression combinations in a similar S-expression format as Dfg already produces with `--dump-dfg-stats`. These dumps are not produced by just `--stats` as they are fairly expensive to compute. Currently the new option will dump at two points: just before we change to C types via widthMin usage, and just before emit.
27 lines
720 B
Systemverilog
27 lines
720 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input wire [3:0] a,
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input wire [3:0] b,
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input wire [3:0] c,
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output wire [10:0] o
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);
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wire [3:0] x = ~a & ~b;
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wire [3:0] y = ~b & ~c;
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wire [3:0] z = ~c & ~a;
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wire [0:0] w1 = x[0];
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wire [7:0] w8 = {8{x[1]}};
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wire [15:0] w16 = {2{w8}};
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wire [31:0] w32 = {2{w16}};
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wire [63:0] w64a = {2{w32}};
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wire [63:0] w64b = {2{~w32}};
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wire [62:0] w63 = 63'({2{~w32}});
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wire [95:0] w96 = 96'(w64a);
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assign o = {^x, ^y, ^z, ^w1, ^w8, ^w16, ^w32, ^w64a, ^w64b, ^w63, ^w96};
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endmodule
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