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76 lines
2.5 KiB
Systemverilog
76 lines
2.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(g,e) do if ((g) !== (e)) begin $write("%%Error: %s:%0d: got=%x exp=%x\n", `__FILE__,`__LINE__, (g),(e)); `stop; end while(0)
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// verilog_format: on
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module t;
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int a[1] /* verilator forceable */ = '{0};
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int b[1];
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int old_value;
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typedef bit [6:0] narrow_t[3:1];
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typedef bit [64:0] wide_t[2:3];
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typedef bit [20:0] narrow_packed_t;
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typedef bit [129:0] wide_packed_t;
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narrow_t narrow_array /* verilator forceable */;
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narrow_t narrow_source;
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wide_t wide_array /* verilator forceable */;
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wide_t wide_source;
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narrow_packed_t narrow_expected;
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narrow_packed_t narrow_sampled;
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wide_packed_t wide_expected;
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wide_packed_t wide_sampled;
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bit [64:0] force_value;
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initial begin
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// A whole-array write must not overwrite the value captured in the Preponed region.
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b[0] = 7;
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#1;
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a = b;
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old_value = $sampled(int'({>>{a}}));
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`checkh(old_value, 0);
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old_value = int'({>>{a}});
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`checkh(old_value, 7);
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for (int cycle = 0; cycle < 6; ++cycle) begin
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foreach (narrow_source[i]) narrow_source[i] = 7'(cycle * 13 + i);
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foreach (wide_source[i]) begin
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wide_source[i] = 65'h1_1234_5678_9abc_def0 ^ 65'(cycle * 7 + i);
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end
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force_value = 65'h1_fedc_ba98_7654_3210 ^ 65'(cycle);
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if (cycle == 2) begin
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force narrow_array[2] = force_value[6:0];
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force wide_array[3] = force_value;
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end
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if (cycle == 4) begin
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release narrow_array[2];
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release wide_array[3];
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end
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#1;
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narrow_expected = {>>{narrow_array}};
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wide_expected = {>>{wide_array}};
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narrow_array = narrow_source;
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wide_array = wide_source;
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narrow_sampled = $sampled(narrow_packed_t'({>>{narrow_array}}));
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wide_sampled = $sampled(wide_packed_t'({>>{wide_array}}));
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`checkh(narrow_sampled, narrow_expected);
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`checkh(wide_sampled, wide_expected);
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// Repeated reads share the sample and must stay stable after another write.
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narrow_array = '{default: '0};
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wide_array = '{default: '0};
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narrow_sampled = $sampled(narrow_packed_t'({>>{narrow_array}}));
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wide_sampled = $sampled(wide_packed_t'({>>{wide_array}}));
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`checkh(narrow_sampled, narrow_expected);
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`checkh(wide_sampled, wide_expected);
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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