11 lines
310 B
Verilog
11 lines
310 B
Verilog
// -*- Verilog -*-
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// lib.map file:
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library nonelib none.sv, none*.sv, none/; // no matches
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