45 lines
1009 B
Systemverilog
45 lines
1009 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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// verilog_format: off
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`define stop $stop
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`define check(got,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: time=%t got='h%x exp='h%x\n", `__FILE__,`__LINE__, $time, (got), (exp)); `stop; end while(0)
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// verilog_format: on
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module top;
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logic clk = 0;
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always #5 clk = ~clk;
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int a = 0;
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int b;
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always begin
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$display("%2t Waiting for 'a'", $time);
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@a;
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b = a + 10;
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end
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always @(posedge clk) begin
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++a;
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end
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always @(posedge clk) begin
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#0;
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$display("%2t a=%2d b=%2d", $time, a, b);
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`check(b, a + 10);
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end
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initial begin
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#99;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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