39 lines
972 B
Systemverilog
39 lines
972 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 jalcim
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// SPDX-License-Identifier: CC0-1.0
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// Recursive constant function defined at file scope ($unit).
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// Without the V3Scope.cpp fix, this triggers:
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// %Error: Internal Error: V3Scope.cpp: No clone for package function
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function automatic integer gate_depth;
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input integer way;
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integer d1, d2, sc, n1, n2;
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begin
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if (way <= 1) gate_depth = 0;
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else if (way <= 4) gate_depth = 1;
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else begin
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sc = $clog2(way);
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n1 = 1 << (sc - 1);
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n2 = way - n1;
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d1 = gate_depth(n1);
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d2 = gate_depth(n2);
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gate_depth = ((d1 > d2) ? d1 : d2) + 1;
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end
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end
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endfunction
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module t;
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localparam D5 = gate_depth(5);
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localparam D8 = gate_depth(8);
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initial begin
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if (D5 !== 2) $stop;
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if (D8 !== 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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