94 lines
2.4 KiB
Systemverilog
94 lines
2.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2003 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc;
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initial cyc = 1;
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reg [15:0] m_din;
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// We expect all these blocks should split;
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// blocks that don't split should go in t_alw_nosplit.v
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reg [15:0] a_split_1, a_split_2;
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always @( /*AS*/ m_din) begin
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a_split_1 = m_din;
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a_split_2 = m_din;
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end
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reg [15:0] d_split_1, d_split_2;
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always @(posedge clk) begin
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d_split_1 <= m_din;
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d_split_2 <= d_split_1;
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d_split_1 <= ~m_din;
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end
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reg [15:0] h_split_1;
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reg [15:0] h_split_2;
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always @(posedge clk) begin
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// $write(" cyc = %x m_din = %x\n", cyc, m_din);
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if (cyc > 2) begin
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if (m_din == 16'h0) begin
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h_split_1 <= 16'h0;
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h_split_2 <= 16'h0;
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end
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else begin
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h_split_1 <= m_din;
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h_split_2 <= ~m_din;
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end
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end
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else begin
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h_split_1 <= 16'h0;
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h_split_2 <= 16'h0;
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end
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end
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reg [15:0] l_split_1, l_split_2;
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always @(posedge clk) begin
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l_split_2 <= l_split_1;
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l_split_1 <= l_split_2 | m_din;
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end
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// (The checker block is an exception, it won't split.)
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always @(posedge clk) begin
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if (cyc != 0) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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m_din <= 16'hfeed;
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end
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if (cyc == 3) begin
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end
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if (cyc == 4) begin
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m_din <= 16'he11e;
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//$write(" A %x %x\n", a_split_1, a_split_2);
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if (!(a_split_1 == 16'hfeed && a_split_2 == 16'hfeed)) $stop;
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if (!(d_split_1 == 16'h0112 && d_split_2 == 16'h0112)) $stop;
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if (!(h_split_1 == 16'hfeed && h_split_2 == 16'h0112)) $stop;
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end
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if (cyc == 5) begin
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m_din <= 16'he22e;
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if (!(a_split_1 == 16'he11e && a_split_2 == 16'he11e)) $stop;
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if (!(d_split_1 == 16'h0112 && d_split_2 == 16'h0112)) $stop;
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if (!(h_split_1 == 16'hfeed && h_split_2 == 16'h0112)) $stop;
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end
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if (cyc == 6) begin
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m_din <= 16'he33e;
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if (!(a_split_1 == 16'he22e && a_split_2 == 16'he22e)) $stop;
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if (!(d_split_1 == 16'h1ee1 && d_split_2 == 16'h0112)) $stop;
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if (!(h_split_1 == 16'he11e && h_split_2 == 16'h1ee1)) $stop;
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end
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if (cyc == 7) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end // always @ (posedge clk)
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endmodule
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