35 lines
841 B
Systemverilog
35 lines
841 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Nikolai Kumar
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(g,e) do if ((g) !== (e)) begin $write("%%Error: %s:%0d: got=%x exp=%x\n", `__FILE__,`__LINE__, (g),(e)); `stop; end while(0)
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// verilog_format: on
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module t;
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logic var_en[0:1] /*verilator forceable*/;
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logic sig;
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initial begin
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var_en[0] = 1'b0;
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var_en[1] = 1'b0;
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end
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//verilator lint_off IEEEMAYDEPRECATE
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initial assign sig = 1'b1;
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//verilator lint_on IEEEMAYDEPRECATE
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initial begin
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#1;
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force var_en[0] = 1'b1;
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#1;
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`checkh(var_en[0], 1'b1);
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`checkh(var_en[1], 1'b0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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