verilator/test_regress/t/t_clocking_default_bad.out

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%Error: t/t_clocking_default_bad.v:13:12: Only one default clocking block allowed per module (IEEE 1800-2023 14.12)
: ... note: In instance 't'
13 | clocking cb2 @(negedge clk);
| ^~~
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to