31 lines
846 B
Systemverilog
31 lines
846 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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// verilog_format: on
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class num_gen;
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function int get_num(int x);
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return x;
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endfunction
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endclass
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module t;
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num_gen gen;
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bit [4:0] arr[];
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initial begin
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gen = new;
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arr = new[1];
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arr[0][gen.get_num(3)] = 1'b1;
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`checkh(arr[0][3],1'b1);
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$finish;
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end
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endmodule
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