29 lines
1.1 KiB
Systemverilog
29 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`ifdef verilator
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`verilator_config
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lint_off -rule DECLFILENAME
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// Test overlapping ranges work correctly
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lint_off -rule UNUSED -file "*/t_*" -lines 21-23
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lint_off -rule UNUSED -file "*/t_*" -lines 20-22 // Intentional overlap with above
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lint_off -rule UNUSED -file "*/t_*" -lines 25-99
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lint_on -rule UNUSED -file "*/t_*" -lines 26
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`verilog
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`endif
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module t;
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reg unuse_warn_var_line20; // Unused warning - must be line 20
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reg unuse_warn2_var_line21; // Unused warning - must be line 21
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reg unuse_warn3_var_line22; // Unused warning - must be line 22
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reg unuse_warn4_var_line23; // Unused warning - must be line 23
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reg unuse_warn5_var_line24; // Unused warning - must be line 24 (not suppressed)
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reg unuse_warn5_var_line25; // Unused warning - must be line 25
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reg unuse_warn5_var_line26; // Unused warning - must be line 26 (turned on)
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reg unuse_warn5_var_line27; // Unused warning - must be line 27
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endmodule
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