57 lines
1.1 KiB
Systemverilog
57 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Luca Colagrande.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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localparam logic [1:0] INST1 = 2'b0?;
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localparam logic [1:0] INST2 = 2'b0?;
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localparam logic [1:0] INST3 = 2'b1?;
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logic [1:0] in, out;
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always_comb begin
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unique casez (in)
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INST1, INST2: begin
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if (in == 2'b00) out = 2'b01;
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else out = 2'b00;
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end
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INST3: begin
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out = 2'b10;
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end
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default: begin
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out = 2'b11;
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end
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endcase
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end
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] in=%x out=%x\n", $time, in, out);
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`endif
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if (in == 0) begin
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if (out != 2'b01) $stop;
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end
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else if (in == 1) begin
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if (out != 2'b00) $stop;
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end
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else if (in == 2) begin
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if (out != 2'b10) $stop;
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end
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else if (in == 3) begin
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if (out != 2'b10) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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in <= in + 1;
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end
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endmodule
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