21 lines
667 B
Python
21 lines
667 B
Python
#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.top_filename = "t/t_opt_slice_element_limit.v"
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test.compile(verilator_flags2=['--stats', '--fslice-element-limit', '10'])
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test.file_grep(test.stats, r'Optimizations, Slice array skips due to size limit\s+(\d+)', 4)
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test.passes()
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