19 lines
438 B
Systemverilog
19 lines
438 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// Test that a standalone primitive can be a top level module
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primitive p(output id_2, input id_1);
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table
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1 : 0;
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0 : 1;
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endtable
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endprimitive
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module t; // Overridden by --top-module
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initial $stop;
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endmodule
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