42 lines
850 B
Systemverilog
42 lines
850 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by PlanV GmbH.
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// SPDX-License-Identifier: CC0-1.0
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module t_scope_std_randomize;
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bit [7:0] addr;
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bit [15:0] data;
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function bit run();
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int ready;
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int success;
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bit [7:0] old_addr;
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bit [15:0] old_data;
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int old_ready;
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old_addr = addr;
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old_data = data;
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old_ready = ready;
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success = randomize(addr, ready); // std::randomize
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if (success == 0) return 0;
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if (addr == old_addr && data != old_data && ready == old_ready) begin
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return 0;
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end
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return 1;
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endfunction
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initial begin
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bit ok = 0;
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int success;
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ok = 0;
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ok = run();
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if (!ok) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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