34 lines
590 B
Systemverilog
34 lines
590 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2025 by Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module child (
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input logic test_out
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);
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initial begin
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#1;
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if (test_out != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module parent;
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logic [1:0] test_out;
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child u0 (.test_out(test_out[0]));
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endmodule
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interface my_if;
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initial begin
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t.test_parent.test_out = 1;
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end
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endinterface
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module t;
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parent test_parent ();
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my_if intf ();
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endmodule
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