48 lines
982 B
Systemverilog
48 lines
982 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module p_i_match #(
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parameter type S_IS_T,
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parameter S_IS_T S_IS
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) ();
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endmodule
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module ring #(
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parameter type I_T
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) ();
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localparam int unsigned N_SS = (18 / 2) / 2;
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localparam int unsigned N_P_IS = (18 / 2) - 1;
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typedef int s_is_t[N_P_IS-1:0];
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function automatic s_is_t gen_s_is();
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for (int st = 0; st < N_SS; st++) begin
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for (int i = 0; i < 2; i++) begin
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if (st * 2 + i < N_P_IS) begin
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int delta = ((st + 1) * 2) + i;
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gen_s_is[st*2+i] = i;
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end
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end
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end
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endfunction
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localparam s_is_t S_IS = gen_s_is();
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p_i_match #(
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.S_IS_T(s_is_t),
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.S_IS(S_IS)
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) p (
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.*);
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endmodule
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module t;
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typedef logic [4:0] i_t;
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ring #(
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.I_T(i_t)
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) dut (
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.*);
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endmodule
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