21 lines
442 B
Systemverilog
21 lines
442 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2017 by Johan Bjork.
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// SPDX-License-Identifier: CC0-1.0
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module t ();
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simple_bus sb_intf ();
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simple_bus #(.PARAMETER(sb_intf.dummy)) simple ();
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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interface simple_bus #(
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PARAMETER = 0
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);
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logic dummy;
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endinterface
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