31 lines
673 B
Systemverilog
31 lines
673 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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interface inf;
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int v;
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endinterface
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module GenericModule (interface a, inf b, interface c);
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initial begin
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#1;
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if (a.v != 7) $stop;
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if (b.v != 8) $stop;
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if (c.v != 9) $stop;
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end
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endmodule
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module t;
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inf inf_inst[3]();
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GenericModule genericModule (inf_inst[0], inf_inst[1], inf_inst[2]);
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initial begin
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inf_inst[0].v = 7;
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inf_inst[1].v = 8;
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inf_inst[2].v = 9;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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