45 lines
1.3 KiB
Systemverilog
45 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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module t;
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function automatic int recurse_self;
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input int i;
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int r1;
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int r2;
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// Simulator support for statics in constant functions get varying results, not testing
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static int local_static = 10;
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automatic int local_automatic; // check each function call resets to zero
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if (i == 0) begin
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local_static = 0;
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recurse_self = 0;
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end
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else begin
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local_static = local_static + 1;
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local_automatic = local_automatic + 10;
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recurse_self = i + recurse_self(i - 1) * 2 + recurse_self(i - 1) * 3 + local_automatic;
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end
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endfunction
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localparam int F0 = recurse_self(0);
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localparam int F3 = recurse_self(3);
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localparam int F4 = recurse_self(4);
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initial begin
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`checkd(F0, 0);
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`checkd(F3, 348);
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`checkd(F4, 1754);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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