54 lines
1.2 KiB
Systemverilog
54 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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`define check_rand(cl, field, cond) \
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begin \
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longint prev_result; \
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int ok = 0; \
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if (!bit'(cl.randomize())) $stop; \
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prev_result = longint'(field); \
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if (!(cond)) $stop; \
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repeat(9) begin \
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longint result; \
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if (!bit'(cl.randomize())) $stop; \
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result = longint'(field); \
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if (!(cond)) $stop; \
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if (result != prev_result) ok = 1; \
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prev_result = result; \
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end \
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if (ok != 1) $stop; \
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end
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class Rand1;
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rand bit [4:0] x;
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constraint c {$countones(x) == 1;}
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endclass
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class Rand2;
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rand bit [5:0] x;
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rand bit [2:0] y;
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constraint c {10'b1 + 10'($countones(x + 6'(y))) == 3;}
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endclass
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class Rand3;
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rand bit [32:0] x;
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constraint c {$countones(x) == 1;}
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endclass
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module t;
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Rand1 r1 = new;
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Rand2 r2 = new;
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Rand3 r3 = new;
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initial begin
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`check_rand(r1, r1.x, $countones(r1.x) == 1);
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`check_rand(r2, r2.x, 10'b1 + 10'($countones(r2.x + 6'(r2.y))) == 3);
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`check_rand(r3, r3.x, $countones(r3.x) == 1);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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