34 lines
605 B
Systemverilog
34 lines
605 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class factory #(type T);
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static function T create;
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T obj = new;
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return obj;
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endfunction
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endclass
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class foo;
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endclass
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class bar extends foo;
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static function bar create;
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bar b = new;
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return b;
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endfunction
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endclass
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module t;
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initial begin
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foo f;
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if (bit'($random))
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f = bar::create;
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else
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f = factory#(foo)::create();
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$finish;
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end
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endmodule;
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