54 lines
1.0 KiB
Systemverilog
54 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class ClsNoArg;
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int imembera;
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function new();
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imembera = 5;
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endfunction
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endclass
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class ClsNoNew;
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int imembera;
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endclass
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class ClsArg;
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int imembera;
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function new(int i);
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imembera = i + 1;
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endfunction
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endclass
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class ClsNew1;
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static function new(); // <--- Error: new can't be static
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endfunction
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endclass
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class ClsNew2;
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virtual function new(); // <--- Error: new can't be virtual
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endfunction
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endclass
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class ClsNew3;
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extern virtual function new(); // <--- Error: new can't be virtual
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endclass
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function ClsNew3::new();
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endfunction
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module t;
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initial begin
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ClsNoArg c1;
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ClsNoNew c2;
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ClsArg c3;
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c1 = new(3); // Bad, called with arg
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c2 = new(3); // Bad, called with arg
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c3 = new(); // Bad, called without arg
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c1 = new[2];
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$stop;
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end
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endmodule
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