35 lines
784 B
Systemverilog
35 lines
784 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module m();
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class c;
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static function void fstatic();
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`checkh(v, 42);
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v++;
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endfunction
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function void fnonstatic();
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`checkh(v, 43);
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v++;
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endfunction
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endclass
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c classinst;
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int v;
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initial begin
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v=42;
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`checkh(v, 42);
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c::fstatic();
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classinst = new();
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classinst.fnonstatic();
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`checkh(v, 44);
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$finish;
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end
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endmodule
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