20 lines
545 B
Systemverilog
20 lines
545 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2020 Geza Lore
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module t_x_assign (
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input wire clk,
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output reg o,
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output reg [31:0] o_int
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);
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always @(posedge clk) begin
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if (1'bx) o <= 1'd1;
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else o <= 1'd0;
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o_int <= 'x;
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end
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endmodule
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