81 lines
1.6 KiB
Systemverilog
81 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilator lint_off ZERODLY
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interface my_if ();
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logic clk;
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realtime clk_period;
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bit clk_active = 0;
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initial begin
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wait (clk_active);
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forever begin
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#(clk_period);
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if (clk_active) begin
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case (clk)
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1'b0: clk = 1'b1;
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default: clk = 1'b0;
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endcase
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end
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end
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end
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// always @* with process::self() must not become a spinning coroutine
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always @* begin
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if (clk_active && clk_period == 0.0) begin
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automatic process p = process::self();
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$display("%m: active with 0 period (proc=%p)", p);
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$stop;
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end
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end
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function void set_period(realtime p);
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clk_period = p;
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endfunction
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function void start_clk();
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if (clk_period) clk_active = 1;
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endfunction
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endinterface
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class Driver;
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virtual my_if vif;
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task run();
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vif.set_period(5);
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#10;
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vif.start_clk();
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endtask
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endclass
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module t;
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my_if intf ();
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// Verify combinational always with timing controls still works as coroutine
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int combo_timing_count = 0;
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always @* begin
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combo_timing_count = combo_timing_count + 1;
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#1;
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end
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initial begin
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automatic Driver d = new;
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d.vif = intf;
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d.run();
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repeat (4) @(posedge intf.clk);
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if (combo_timing_count == 0) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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initial begin
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#1000;
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$display("TIMEOUT");
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$stop;
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end
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endmodule
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