44 lines
998 B
Systemverilog
44 lines
998 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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interface AXIS_IF (
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input logic aclk
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);
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logic [127:0] tdata;
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logic [ 31:0] tuser;
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logic tvalid, tready;
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modport master(input aclk, output tdata, tuser, tvalid, input tready);
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modport slave(input aclk, input tdata, tuser, tvalid, output tready);
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endinterface : AXIS_IF
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module sub (
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input clk,
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AXIS_IF.slave s_axis_if
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);
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assign s_axis_if.tready = s_axis_if.tdata[0];
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endmodule
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module dut (
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input clk,
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AXIS_IF.slave s_axis_if
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);
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sub u_sub(.*);
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endmodule
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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AXIS_IF s_axis_if (.aclk(clk));
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dut u_dut (.clk, .s_axis_if(s_axis_if));
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initial begin
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$c("Verilated::scopesDump();");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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