32 lines
537 B
Systemverilog
32 lines
537 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// SPDX-FileCopyrightText: 2020 Wilson Snyder and Marlon James
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic clk;
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initial begin
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clk = 0;
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#10;
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while ($time < 100) begin
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clk = !clk;
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#10;
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end
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end
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reg [31:0] count /*verilator public_flat_rd */;
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// Test loop
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initial begin
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count = 0;
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end
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always @(posedge clk) begin
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count <= count + 2;
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end
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endmodule
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