24 lines
828 B
Systemverilog
24 lines
828 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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`ifdef verilator
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`verilator_config
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lint_off -rule DECLFILENAME
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// Test filename matches are in directive parse order
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lint_off -rule UNUSED -file "*/t_*" // Sorts before t_vlt_*
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lint_off -rule UNUSED -file "*/t_vlt_warn*" // Sorts after t_vlt_*
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lint_on -rule UNUSED -file "*/t_vlt_*"
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lint_off -rule UNUSED -file "*/t_vlt_warn*" -lines 21-22
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`verilog
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`endif
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module t;
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reg unuse_warn_var_line20; // Unused warning - must be line 20 (on)
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reg unuse_warn2_var_line21; // Unused warning - must be line 21 (off)
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reg unuse_warn3_var_line22; // Unused warning - must be line 22 (off)
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endmodule
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