18 lines
561 B
Plaintext
18 lines
561 B
Plaintext
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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`verilator_config
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public_flat_rd -module "top" -param "*"
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public_flat_rw -module "top" -port "*"
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public_flat_rd -module "mid" -param "*"
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public_flat_rw -module "mid" -function "*" -port "top_f_port_o"
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public_flat -module "mid" -var "mid_tmp_b"
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public_flat -module "sub" -port "*"
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public_flat_rd -module "sub" -function "*" -param "SUB_F_LOCALPARAM"
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