12 lines
288 B
Systemverilog
12 lines
288 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk /*verilator clock_enable*/
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);
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initial $finish;
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endmodule
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