44 lines
948 B
Systemverilog
44 lines
948 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2017 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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class Rnd;
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rand bit x;
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endclass
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module t (
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input clk
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);
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Rnd c;
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int cyc;
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integer rand_result;
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integer seed = 123;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc != 0) begin
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if (cyc == 10) begin
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#5;
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$display("dist: %f ", $dist_poisson(seed, 12)); // Get verilated_probdist.cpp
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c = new;
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rand_result = c.randomize();
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$display("rand: %x x: %x ", rand_result, c.x); // Get verilated_random.cpp
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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cyc_eq_5 :
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cover property (@(posedge clk) cyc == 5) $display("*COVER: Cyc==5");
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export "DPI-C" function dpix_f_int;
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function int dpix_f_int();
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return cyc;
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endfunction
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endmodule
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