46 lines
1012 B
Systemverilog
46 lines
1012 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2010 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// bug291
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module t (
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input clk
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);
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integer out18;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire out1; // From test of Test.v
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wire out19; // From test of Test.v
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wire out1b; // From test of Test.v
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// End of automatics
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Test test ( /*AUTOINST*/
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// Outputs
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.out1(out1),
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.out18(out18),
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.out1b(out1b),
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.out19(out19)
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);
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// Test loop
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always @(posedge clk) begin
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if (out1 !== 1'b1) $stop;
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if (out18 !== 32'h18) $stop;
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if (out1b !== 1'b1) $stop;
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if (out19 !== 1'b1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module Test (
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output wire out1 = 1'b1,
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output integer out18 = 32'h18,
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output var out1b = 1'b1,
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output var logic out19 = 1'b1
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);
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endmodule
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