203 lines
5.4 KiB
Systemverilog
203 lines
5.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2008 Lane Brooks
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// SPDX-License-Identifier: CC0-1.0
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module t ( /*AUTOARG*/
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// Outputs
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o_29, o_29_old, o_30, o_30_old, o_31, o_31_old, o_32, o_32_old, o_59,
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o_59_old, o_60, o_60_old, o_62, o_62_old, o_64, o_64_old, o_119, o_119_old,
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o_120, o_120_old, o_121, o_121_old, o_127, o_127_old, o_128, o_128_old, o_255,
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o_255_old, o_256, o_256_old,
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// Inputs
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i_29, i_29_old, i_30, i_30_old, i_31, i_31_old, i_32, i_32_old, i_59,
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i_59_old, i_60, i_60_old, i_62, i_62_old, i_64, i_64_old, i_119, i_119_old,
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i_120, i_120_old, i_121, i_121_old, i_127, i_127_old, i_128, i_128_old, i_255,
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i_255_old, i_256, i_256_old
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);
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input [255:0] i_29;
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output wire [255:0] o_29;
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input [255:0] i_29_old;
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output wire [255:0] o_29_old;
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input [255:0] i_30;
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output wire [255:0] o_30;
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input [255:0] i_30_old;
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output wire [255:0] o_30_old;
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input [255:0] i_31;
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output wire [255:0] o_31;
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input [255:0] i_31_old;
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output wire [255:0] o_31_old;
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input [255:0] i_32;
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output wire [255:0] o_32;
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input [255:0] i_32_old;
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output wire [255:0] o_32_old;
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input [255:0] i_59;
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output wire [255:0] o_59;
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input [255:0] i_59_old;
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output wire [255:0] o_59_old;
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input [255:0] i_60;
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output wire [255:0] o_60;
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input [255:0] i_60_old;
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output wire [255:0] o_60_old;
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input [255:0] i_62;
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output wire [255:0] o_62;
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input [255:0] i_62_old;
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output wire [255:0] o_62_old;
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input [255:0] i_64;
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output wire [255:0] o_64;
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input [255:0] i_64_old;
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output wire [255:0] o_64_old;
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input [255:0] i_119;
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output wire [255:0] o_119;
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input [255:0] i_119_old;
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output wire [255:0] o_119_old;
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input [255:0] i_120;
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output wire [255:0] o_120;
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input [255:0] i_120_old;
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output wire [255:0] o_120_old;
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input [255:0] i_121;
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output wire [255:0] o_121;
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input [255:0] i_121_old;
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output wire [255:0] o_121_old;
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input [255:0] i_127;
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output wire [255:0] o_127;
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input [255:0] i_127_old;
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output wire [255:0] o_127_old;
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input [255:0] i_128;
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output wire [255:0] o_128;
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input [255:0] i_128_old;
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output wire [255:0] o_128_old;
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input [255:0] i_255;
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output wire [255:0] o_255;
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input [255:0] i_255_old;
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output wire [255:0] o_255_old;
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input [255:0] i_256;
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output wire [255:0] o_256;
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input [255:0] i_256_old;
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output wire [255:0] o_256_old;
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sub sub (.*);
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endmodule
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module sub ( /*AUTOARG*/
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// Outputs
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o_29, o_29_old, o_30, o_30_old, o_31, o_31_old, o_32, o_32_old, o_59,
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o_59_old, o_60, o_60_old, o_62, o_62_old, o_64, o_64_old, o_119, o_119_old,
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o_120, o_120_old, o_121, o_121_old, o_127, o_127_old, o_128, o_128_old, o_255,
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o_255_old, o_256, o_256_old,
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// Inputs
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i_29, i_29_old, i_30, i_30_old, i_31, i_31_old, i_32, i_32_old, i_59,
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i_59_old, i_60, i_60_old, i_62, i_62_old, i_64, i_64_old, i_119, i_119_old,
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i_120, i_120_old, i_121, i_121_old, i_127, i_127_old, i_128, i_128_old, i_255,
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i_255_old, i_256, i_256_old
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);
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input [255:0] i_29;
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output wire [255:0] o_29;
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input [255:0] i_29_old;
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output wire [255:0] o_29_old;
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input [255:0] i_30;
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output wire [255:0] o_30;
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input [255:0] i_30_old;
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output wire [255:0] o_30_old;
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input [255:0] i_31;
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output wire [255:0] o_31;
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input [255:0] i_31_old;
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output wire [255:0] o_31_old;
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input [255:0] i_32;
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output wire [255:0] o_32;
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input [255:0] i_32_old;
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output wire [255:0] o_32_old;
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input [255:0] i_59;
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output wire [255:0] o_59;
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input [255:0] i_59_old;
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output wire [255:0] o_59_old;
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input [255:0] i_60;
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output wire [255:0] o_60;
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input [255:0] i_60_old;
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output wire [255:0] o_60_old;
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input [255:0] i_62;
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output wire [255:0] o_62;
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input [255:0] i_62_old;
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output wire [255:0] o_62_old;
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input [255:0] i_64;
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output wire [255:0] o_64;
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input [255:0] i_64_old;
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output wire [255:0] o_64_old;
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input [255:0] i_119;
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output wire [255:0] o_119;
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input [255:0] i_119_old;
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output wire [255:0] o_119_old;
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input [255:0] i_120;
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output wire [255:0] o_120;
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input [255:0] i_120_old;
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output wire [255:0] o_120_old;
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input [255:0] i_121;
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output wire [255:0] o_121;
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input [255:0] i_121_old;
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output wire [255:0] o_121_old;
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input [255:0] i_127;
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output wire [255:0] o_127;
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input [255:0] i_127_old;
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output wire [255:0] o_127_old;
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input [255:0] i_128;
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output wire [255:0] o_128;
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input [255:0] i_128_old;
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output wire [255:0] o_128_old;
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input [255:0] i_255;
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output wire [255:0] o_255;
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input [255:0] i_255_old;
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output wire [255:0] o_255_old;
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input [255:0] i_256;
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output wire [255:0] o_256;
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input [255:0] i_256_old;
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output wire [255:0] o_256_old;
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assign o_29 = i_29;
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assign o_29_old = i_29_old;
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assign o_30 = i_30;
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assign o_30_old = i_30_old;
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assign o_31 = i_31;
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assign o_31_old = i_31_old;
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assign o_32 = i_32;
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assign o_32_old = i_32_old;
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assign o_59 = i_59;
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assign o_59_old = i_59_old;
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assign o_60 = i_60;
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assign o_60_old = i_60_old;
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assign o_62 = i_62;
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assign o_62_old = i_62_old;
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assign o_64 = i_64;
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assign o_64_old = i_64_old;
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assign o_119 = i_119;
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assign o_119_old = i_119_old;
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assign o_120 = i_120;
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assign o_120_old = i_120_old;
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assign o_121 = i_121;
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assign o_121_old = i_121_old;
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assign o_127 = i_127;
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assign o_127_old = i_127_old;
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assign o_128 = i_128;
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assign o_128_old = i_128_old;
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assign o_255 = i_255;
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assign o_255_old = i_255_old;
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assign o_256 = i_256;
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assign o_256_old = i_256_old;
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endmodule
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