16 lines
450 B
Plaintext
16 lines
450 B
Plaintext
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2019 Stefan Wallentowitz
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// SPDX-License-Identifier: CC0-1.0
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`verilator_config
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sc_bv -module "t" -var "ibv1_vlt"
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sc_bv -module "*" -var "ibv16_vlt"
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sc_bv -module "*" -var "obv*_vlt"
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sc_biguint -module "t" -var "ibu1_vlt"
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sc_biguint -module "*" -var "ibu16_vlt"
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sc_biguint -module "*" -var "obu*_vlt"
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