16 lines
326 B
Systemverilog
16 lines
326 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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output logic [64:0] output_vec[257]
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);
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assign output_vec = '{default: 1};
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initial $finish;
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endmodule
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